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| MC54/74F74 DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP The MC54/74F74 is a dual D-type flip-flop with Direct Clear and Set inputs and complementary (Q, Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. After the Clock Pulse input threshold voltage has been passed, the Data input is locked out and information present will not be transferred to the outputs until the next rising edge of the Clock Pulse input. DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP FASTTM SCHOTTKY TTL * ESD > 4000 Volts J SUFFIX CERAMIC CASE 632-08 14 1 CONNECTION DIAGRAM VCC 14 CD2 13 D2 12 CP2 11 SD2 10 Q2 9 Q2 8 D1 CD1 Q1 CP1 SD1 Q1 CP2 SD2 Q2 D2 CD2 Q2 14 N SUFFIX PLASTIC CASE 646-06 1 1 CD1 2 D1 3 CP1 4 SD1 5 Q1 6 Q1 7 GND 14 1 D SUFFIX SOIC CASE 751A-02 FUNCTION TABLE (Each Half) Input @ tn D L H Asynchronous Inputs: LOW Input to SD sets Q to HIGH level LOW Input to CD sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both Q and Q HIGH H = HIGH Voltage Level L = LOW Voltage Level tn = Bit time before clock pulse tn + 1 = Bit time after clock pulse Outputs @ tn + 1 Q L H Q H L ORDERING INFORMATION MC54FXXJ MC74FXXN MC74FXXD Ceramic Plastic SOIC LOGIC SYMBOL 4 2 3 SD1 D1 Q1 CP1 Q1 CD1 1 VCC = PIN 14 GND = PIN 7 6 10 SD2 D2 Q2 CP2 Q2 CD2 13 8 5 12 11 9 FAST AND LS TTL DATA 4-33 MC54/74F74 LOGIC DIAGRAM Q Q D CP SD CD NOTE: This diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. GUARANTEED OPERATING RANGES Symbol VCC TA Supply Voltage Operating Ambient Temperature Range Parameter 54, 74 54 74 IOH IOL Output Current -- High Output Current -- Low 54, 74 54, 74 Min 4.50 -55 0 Typ 5.0 25 25 Max 5.50 125 70 -1.0 20 mA mA Unit V C DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage 54, 74 VOH VOL IIH Output HIGH Voltage Output LOW Voltage Input HIGH Current 74 2.5 2.7 3.4 3.4 0.35 0.5 20 100 IIL Input LOW Current (CP and D Inputs) (CD and SD Inputs) IOS ICC Output Short Circuit Current (Note 2) Power Supply Current -60 10.5 -0.6 -1.8 -150 16 Min 2.0 0.8 -1.2 Typ Max Unit V V V V V V A A mA mA mA mA VOUT = 0 V VCP = 0 V VCC = MAX VCC = MAX Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage IIN = -18 mA IOH = -1.0 mA IOH = -1.0 mA IOL = 20mA VIN = 2.7 V VIN = 7.0 V VIN = 0.5V VCC = MAX VCC = MIN VCC = 4.50 V VCC = 4.75 V VCC = MIN VCC = MAX NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under guaranteed operating ranges. 2. Not more then one output should be shorted at a time, nor for more than 1 second. FAST AND LS TTL DATA 4-34 MC54/74F74 AC CHARACTERISTICS 54/74F TA = +25C VCC = +5.0 V CL = 50 pF Symbol fmax tPLH tPHL tPLH tPHL Parameter Maximum Clock Frequency Propagation Delay CPn to Qn or Qn Propagation Delay CDn or SDn to Qn or Qn Min 100 3.8 4.4 2.5 3.5 6.8 8.0 6.1 9.0 Max 54F TA = -55C to +125C VCC = 5.0 V 10% CL = 50 pF Min 100 3.8 4.4 2.5 3.5 8.5 10.5 8.0 11.5 Max 74F TA = 0C to 70C VCC = 5.0 V 10% CL = 50 pF Min 100 3.8 4.4 2.5 3.5 7.8 ns 9.2 7.1 ns 10.5 Max Unit MHz AC OPERATING REQUIREMENTS 54/74F TA = +25C VCC = +5.0 V Symbol ts(H) ts(L) th(H) th(L) tw(H) tw(L) tw(L) trec Parameter Setup Time, HIGH or LOW Dn to CPn Hold Time, HIGH or LOW Dn to CPn CPn Pulse Width, HIGH or LOW CDn or SDn Pulse Width, LOW Recovery Time CDn or SDn to CP Min 2.0 3.0 1.0 1.0 4.0 5.0 4.0 2.0 Typ Max 54F TA = -55C to +125C VCC = 5.0 V 10% Min 3.0 4.0 2.0 2.0 4.0 6.0 4.0 3.0 Max 74F TA = 0C to +70C VCC = 5.0V 10% Min 2.0 3.0 ns 1.0 1.0 4.0 ns 5.0 4.0 2.0 ns ns Max Unit FAST AND LS TTL DATA 4-35 |
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